基于误差估值累加开环校正的诱导式欺骗检测方法

诱导式卫星欺骗干扰可诱导航空器逐渐偏离预定航迹，难以被发现，因此及时有效地检测干扰是飞行安全的保障。在现有紧组合导航体制基础上，设计了一种基于误差估值累加开环校正的紧组合导航结构，并证明了其性能与传统闭环校正紧组合导航性能等效。在此结构中，将紧组合导航系统与自适应序贯概率比检测方法结合，提出了一种基于误差估值累加开环校正的诱导式欺骗检测方法，融合紧组合导航信息与其他不受欺骗影响的导航信息，构建欺骗检测统计量进行诱导式欺骗检测。仿真结果表明，开环校正结构可避免随时间累加的惯性导航系统误差所导致的组合导航滤波器发散问题，同时欺骗检测方法可进一步提高算法对“最坏”情形下微小诱导式欺骗的检测效果。     

Quantum effect of cooling down the environment temperature of mesoscopic LC circuit

We examine the quantum effect of cooling down the environment temperature of mesoscopic LC circuit, and find that the ground state of the circuit is no longer in the thermo vacuum state, but in a negative binomial state. We calculate energy of the circuit in this new state, which increases with the cooling of the environment.     

Modeling and design of 3-D MPPT for ultra low power RF energy harvesters

Radio-Frequency (RF) energy harvesting must cope with the limited availability and high variability of the energy source. In this paper, the modeling of an RF harvester for ultra low power environments is presented. A mathematical model based on theoretical analysis is developed. The model demonstrates that the maximum transferred power point is located in a three-dimensional space defined by the input capacitance, the output voltage, and the load resistance of the rectifier circuit. Moreover, the mathematical model returns results in substantial agreement with the SPICE simulation results, while guaranteeing a remarkable reduction of the required computation time. Furthermore, the paper reports the implementation of a mixed signal system for the 3-D MPPT, to be embedded in an RF harvester, in a 65 nm CMOS technology. The circuit exhibits a simulated power consumption lower than 100 nW, making this solution suitable for ultra low power harvesting.     

A novel minimum weight formulation of topology optimization implemented with reanalysis approach

In this paper, we develop an efficient diagonal quadratic optimization formulation for minimum weight design problem subject to multiple constraints. A high-efficiency computational approach of topology optimization is implemented within the framework of approximate reanalysis. The key point of the formulation is the introduction of the reciprocal-type variables. The topology optimization seeking for minimum weight can be transformed as a sequence of quadratic program with separable and strictly positive definite Hessian matrix, thus can be solved by a sequential quadratic programming approach. A modified sensitivity filtering scheme is suggested to remove undesirable checkerboard patterns and mesh dependence. Several typical examples are provided to validate the presented approach. It is observed that the optimized structure can achieve lighter weight than those from the established method by the demonstrative numerical test. Considerable computational savings can be achieved without loss of accuracy of the final design for 3D structure. Moreover, the effects of multiple constraints and upper bound of the allowable compliance upon the optimized designs are investigated by numerical examples.     

Bayesian Inference for ARFIMA Models

This article develops practical methods for Bayesian inference in the autoregressive fractionally integrated moving average (ARFIMA) model using the exact likelihood function, any proper prior distribution, and time series that may have thousands of observations. These methods utilize sequentially adaptive Bayesian learning, a sequential Monte Carlo algorithm that can exploit massively parallel desktop computing with graphics processing units (GPUs). The article identifies and solves several problems in the computation of the likelihood function that apparently have not been addressed in the literature. Four applications illustrate the utility of the approach. The most ambitious is an ARFIMA(2,d,2) model for the Campito tree ring time series (length 5405), for which the methods developed in the article provide an essentially uncorrelated sample of size 16,384 from the exact posterior distribution in under four hours. Less ambitious applications take as little as 4 minutes without exploiting GPUs.     

Optimal asymmetrical back plane biasing for energy efficient digital circuits in 28 nm UTBB FD-SOI

In this work we propose an optimal back plane biasing (OBB) scheme to be used in a UTBB FD SOI technology that minimizes the energy per operation consumption of sub threshold digital CMOS circuits. By using this OBB scheme, simulations show that more than 30% energy savings can be obtained with low threshold voltage (LVT) devices in comparison with classic symmetric back plane biasing (SBB) schemes. Additionally, this OBB scheme allows to adjust the performance of the circuit with very small energy penalties. A very simple and intuitive model, for sub threshold digital CMOS circuits, was developed to justify the benefits obtained by OBB. The results predicted by the model are confirmed with extensive simulation results. We show that the OBB approach can be applied easily to a given circuit just based on the information provided by a logic simulation of the circuit (or even an analysis of its structure) and simple electrical simulations of the pMOS and nMOS transistors. Finally, we show that the variability in the energy consumption is improved by using OBB and suggests that new sizing methodologies must be studied to fully benefit from the wide back plane voltage range available in UTBB FD SOI technology for the design of robust energy efficient digital circuits.     

螯合树脂塔智能化控制的优化

介绍了螯合树脂塔的工作流程,分析了原控制系统存在的问题,提出了智能化改造方案,达到了预期效果。     

Bootstrap procedures for detecting multiple persistence shifts in heteroskedastic time series

This article proposes new bootstrap procedures for detecting multiple persistence shifts in a time series driven by non-stationary volatility. The assumed volatility process can accommodate discrete breaks, smooth transition variation as well as trending volatility. We develop wild bootstrap sup-Wald tests of the null hypothesis that the process is either stationary [I(0)] or has a unit root [I(1)] throughout the sample. We also propose a sequential procedure to estimate the number of persistence breaks based on ordering the regime-specific bootstrap p-values. The asymptotic validity of the advocated procedures is established both under the null of stability and a variety of persistence change alternatives. A comparison with existing tests that assume homoskedasticity illustrates the finite sample improvements offered by our methods. An application to OECD inflation rates highlights the empirical relevance of the proposed approach and weakens the case for persistence change relative to existing procedures.     

一款紧凑增强型可变阻抗电磁带隙结构

基于传统AI-EBG结构,提出了一种小尺寸的增强型电磁带隙结构,实现了从0.5~9.4 GHz的宽频带-40 dB噪声抑制深度,且下截止频率减少到数百MHz,可有效抑制多层PCB板间地弹噪声。文中同时研究了EBG结构在高速电路应用时的信号完整性问题,使用差分信号方案可改善信号完整性。     

Generating synthetic benchmark circuits for accelerated life testing of field programmable gate arrays using genetic algorithm and particle swarm optimization

Accelerated life testing (ALT) of a field programmable gate array (FPGA) requires it to be configured with a circuit that satisfies multiple criteria. Hand-crafting such a circuit is a herculean task as many components of the criteria are orthogonal to each other demanding a complex multivariate optimization. This paper presents an evolutionary algorithm aided by particle swarm optimization methodology to generate synthetic benchmark circuits (SBC) that can be used for ALT of FPGAs. The proposed algorithm was used to generate a SBC for ALT of a commercial FPGA. The generated SBC when compared with a hand-crafted one, demonstrated to be more suitable for ALT, measured in terms of meeting the multiple criteria. The SBC generated by the proposed technique utilizes 8.37% more resources; operates at a maximum frequency which is 40% higher; and has 7.75% higher switching activity than the hand-crafted one reported in the literature. The hand-crafted circuit is very specific to the particular device of that family of FPGAs, whereas the proposed algorithm is device-independent. In addition, it took several man months to hand-craft the SBC, whereas the proposed algorithm took less than half-a-day.